1. Field of the Invention
The present invention relates to a feedforward delta-sigma modulator, and particularly to a feedforward delta-sigma modulator that can implement an adder function required by the feedforward delta-sigma modulator in a charge domain.
2. Description of the Prior Art
When a feedforward delta-sigma modulator implements an adder function in a voltage domain, the feedforward delta-sigma modulator increases power consumption due to utilizing additional operational amplifiers. In addition, because limited bandwidth of the additional operational amplifiers can cause excess loop delay (ELD), performance of the feedforward delta-sigma modulator is decreased.
When a feedforward delta-sigma modulator implements an adder function in a current domain, chip area, power consumption, and complexity of the feedforward delta-sigma modulator are increased because transconductance units of the feedforward delta-sigma modulator need enough linearity to maintain linearity of the feedforward delta-sigma modulator.
When a feedforward delta-sigma modulator utilizes ratios of feedforward capacitors to an integrating capacitor of a last stage integrator to implement feedforward coefficients, the feedforward capacitors become larger with the integrating capacitor because the integrating capacitor is usually very large to meet a low noise requirement, resulting in the feedforward delta-sigma modulator needing larger chip area. In addition, the feedforward capacitors can also increase power consumption of operational amplifiers of the feedforward delta-sigma modulator.
Another feedforward delta-sigma modulator utilizes a multi-input comparator to directly connect all feedforward paths, wherein size ratios of input transistors of the feedforward delta-sigma modulator are used for implementing feedforward coefficients. However, a disadvantage of the feedforward delta-sigma modulator with the multi-input comparator is that each feedforward coefficient is sensitive to a common mode voltage of a corresponding integrator output terminal, so large offsets exist between feedforward coefficients of the feedforward delta-sigma modulator when common mode output voltages of integrators of the feedforward delta-sigma modulator are inconsistent.
In addition, because delay time of a quantizer and an analog-to-digital converter can decrease performance of delta-sigma modulator, and even make loop of the delta-sigma modulator unstable, the prior art utilizes an additional digital-to-analog converter between an input terminal of the quantizer and an output terminal of the delta-sigma modulator to compensate the delay time. However, the additional digital-to-analog converter can increase chip area and power consumption of the delta-sigma modulator.
Therefore, the above mentioned feedforward delta-sigma modulators provided by the prior art are not good enough choices for a user.